Basic RTL Design with FPGA and Cadence Design Flow
Basic RTL Design with FPGA and Cadence Design Flow
August 14 to 18, 2023
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Educating the Educators: MSU-IIT’s Digital Design Training Initiative
Educating the Educators: MSU-IIT’s Digital Design Training Initiative
Article by Mark Eric Andam
A groundbreaking partnership between MSU-IIT’s Center for Integrated Circuits Design and USTP-CDO set the stage for a dynamic 5-day training program. Hosted at the USTP-CDO Campus from August 14 to 18, 2023, the initiative aimed to equip participants with the expertise needed to navigate the intricate world of integrated circuits design and drive innovation.
On the 14th of August 2023, marked a pivotal moment as the training workshop kicked off the RTL Design with FPGA and Cadence Digital Design Flow Training. Held at the Makerspace on the 4th Floor of USTP-CDO's Learning Resources Center, the setting epitomized an environment of exploration and innovation. Faculties from MSU-IIT, including Dr. Harreez Villaruz-Quimque, Dr. Gene Fe Palencia, Asst. Prof. Kevin Maglinte, and Dr. Jefferson A. Hora, took on the role of mentors, guiding participants through the intricacies of digital design. Enhancing the training’s impact, MSEE Students from MSU-IIT—Mike Martin Diangco, Dhondee Mugot, and Robert Comaling—joined forces with Microlab OJTs to facilitate hands-on laboratory activities. This training is attended by faculty members from various universities across Luzon, Visayas and Mindanao.
This initiative was made possible through the collaborative support of the Department of Science and Technology (DOST) and DOST-PCIEERD, in partnership with Cadence.
The event commenced with a warm welcome from Dr. Lory Liza D. Bulay-og, Dean of USTP CDO College of Engineering and Architecture, setting the stage for a collaborative journey. Dr. Desiderio R. Apag III, Chief Administrative Officer of CHED Region X, shared a motivating message, urging faculty participants to maximize their training experience for the greater good of their respective institutions. Mr. Julian Chan, Senior AE manager from Cadence Singapore, contributed an enlightening promotional message on the Cadence Tool, amplifying the training's practicality.
Dr. Jefferson A. Hora, head of CICD and Project Head of CIDR Project 4, formally introduced the workshop, setting a precedent of exploration and growth. Followed by Dr. Harreez Villaruz-Quimque who commenced the training proper by delving into Introduction to Verilog and a Comparative Analysis of Programmable Devices. In the afternoon, participants engaged in laboratory activities focusing on tool familiarization and counters.
Mr. Julian Chan, Senior AE of Cadence Singapore, presenting his promotional message; Dr. Desiderio R. Apag III, Chef Administrative Officer of CHED-X, delivering his motivating message;
Dr. Quimque, one of the lecturers and a faculty of MSU-IIT, jumpstarting the entire training-workshop.
The second day unfolded with Dr. Gene Fe Palencia leading a comprehensive session on Finite State Machines, laying a strong foundation for the days ahead. The afternoon unveiled Verilog HDL coding, an essential aspect of digital design, followed by a hands-on Vending Machine laboratory activity.
Under the guidance of Asst. Prof. Kevin Maglinte, the third day immersed participants in Digital Design Flow, integrating theoretical knowledge with practical skills. The participants honed their proficiency with Cadence tools and executed the Encoder/Decoder design lab activity, bridging theory and application.
The following day, the participants were introduced to Xinyx Design Inc., the industry partner of CIDR Project 4, who launched the "XINYX UNLOCKED" competition. Aligned with the theme "From Problems to Possibilities: Building Tomorrow's Cities Today," the competition embodied the training's ethos.
The training continued with Dr. Jefferson A. Hora's insightful lectures delved into digital full chip design and IC design fabrication. The afternoon saw participants translating theory into practice through FPGA implementation, taking strides towards their capstone projects.
The final day was a culmination of dedication and innovation as participants presented their projects. The spectrum spanned from classic games like Pacman, Tetris, and Pong, to groundbreaking innovations such as a Shooting Target and a Robotic Car with UART Bluetooth Remote Control System.
Dr. Lory Liza D. Bulay-og, representing Atty. Dionel O. Albina, the Chancellor of USTP CDO, underscored the training's transformative impact, officially closing the event. After that, certificates lauding participants' dedication were awarded, with special recognition given to Re-ann Cristine Calimpusan, Kristofer O. Flores, and Susie Maestre for their exemplary performance.
This MSU-IIT and USTP-CDO collaboration exemplifies the potential of shared knowledge and synergy in advancing the future of integrated circuits design. As participants carry forward their insights, they illuminate a path of innovation, poised to redefine technological paradigms.
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