Below is a compilation of the training sessions, workshops, and extension activities organized by the Microelectronics Laboratory since 2010. The Microelectronics Laboratory has actively collaborated with various universities across the Philippines to expand the reach of microelectronics education within the country. Additionally, we've welcomed guest lecturers and professors to raise the quality of microelectronics education to an international level. Through these initiatives, we aim to promote and enhance the understanding of microelectronics among students and educators alike.
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Venue: Conference Room, College of Engineering, MSU-IIT, Iligan City
Course Lecturers:
Dr. Jefferson A. Hora
Dr. Gene Fe Palencia
Dr. Harreez Quimque
Dr. Olga Joy Gerasta
Assoc. Prof. Nieva Mapula
Asst. Prof. Kevin Maglinte
Assit. Prof. Rochelle Sabarillo-Macasero
Course Topics:
Overview of Mixed Signal IC Design
Differences between Analog, Digital and Mixed Signal ICs
Applications of Mixed Signal ICs
Fundamental Concepts in Analog and Digital Circuits
Mixed Signal Design Techniques
Data Converters (ADCs & DACs) — characterizations, sub-blocks & functions
ADC Architectures (Flash, SAR, Pipeline, Sigma-Delta)
DAC Architectures (Binary-Weighted, R-2R Ladder, Sigma-Delta)
Mixed Signal Layout Considerations, Strategies and Techniques
ASIC Design Flow and Methodologies
Chip Design Considerations
Course Learning Outcomes:
Understand the Mixed-Signal System Architecture,
Develop a solid understanding of the basic analog and digital circuit fundamentals,
Learn the various required circuit components and circuit sub-blocks of the data converters,
Gain knowledge about the interaction between analog and digital components,
Explain the various techniques in designing data converters.
Understand trade-offs involved in circuit design, such as speed, power consumptions, resolutions, and noise performance.
Learn the different performance characterization of Data converters: Static and Dynamic performance.
Understand the different frequency domain measures of data converters, such as Signal-to-Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR), Harmonic Distortion, Dynamic Range, etc.
Learn the basic simulation of a 3-bit FLASH ADC,
Experience to integrate the analog and digital blocks of an 8-bit SAR ADC,
Understand the noise sources and noise issues of the mixed-signal circuits,
Gain proficiency in using simulation tools to model and verify the performance of mixed-signal circuits.
Basic Mixed-Signal ASIC Design flow using Industry Standard IC Design Cadence software tools.
University and Industry Participants (a total of 30)
Ateneo de Davao University (1)
Caraga State University Cabadbaran Campus (2)
Caraga State University Main Campus (1)
Colegio De Muntinlupa (1)
Mindanao State University Gensan (1)
Mindanao State University Marawi (3)
Notre Dame of Kidapawan College (1)
Surigao del Norte State University (1)
University of Cebu - Lapulapu & Mandaue (1)
University of Cebu - Main (1)
University of Science and Technology of Southern Philippines - CDO (6)
Xavier University - Ateneo de Cagayan (3)
Saint Peter's College (1)
Cor Jesu College, Inc. (2)
Misamis University (3)
Xinyx Design, Inc. (1)
Tekmark, Inc (1)
Venue: Makerspace, LRC Bldg., USTP-CDO, Cagayan de Oro
Course Lecturers:
Dr. Jefferson A. Hora, MSU-IIT
Dr. Harreez V. Quimque, MSU-IIT
Dr. Gene Fe P. Palencia, MSU-IIT
Asst. Prof. Kevin O. Maglinte, MSEE, MSU-IIT
Course Topics:
Hardware Description Language Overview
Introduction to Verilog
Behavioral Modeling
Compiler Directives
Finite State Machine
ASIC flow
Chip Design Considerations
Course Learning Outcomes:
Describe the key features of HDL
Differentiate Verilog HDL and VHDL
Explain the Digital IC Design Process
Explain the different levels of abstraction
Differentiate the two types of code in most HDL
Differentiate Blocking versus Non-blocking Assignment
Create a basic building block in Verilog: Module
Create a Testbench module
Discuss how to describe a digital circuit using gate-level primitives
Explain combinational logic description in Verilog using behavioral constructs
Develop a system for translating FSM state diagrams into Verilog code
Understand the design process for implementing a digital design onto FPGA
Learn how to use Quartus II to program FPGA
Debug Verilog HDL code
Basic Digital ASIC Design flow using Industry Standard IC Design Cadence software tools
University Participants—Faculty Trainees (a total of 22)
Colegio De Muntinlupa (1)
Cebu Institute of Technology - University (1)
Caraga State University (1)
Mindanao State University Main Campus (3)
Mindanao State University - General Santos (2)
Notre Dame of Midsayap College (1)
University of Cebu - Main campus (2)
University of Cebu-LapuLapu and Mandaue (1)
University of Southern Mindanao (3)
University of Science and Technology in Southern Philippines - CDO (4)
Universidad de Zamboanga (1)
Xavier University-Ateneo De Cagayan (2)
Venue: Virtual/Remote Access
Course Lecturers:
Dr. Jefferson A. Hora, PECE
Dr. Gene Fe Palencia
Assoc. Prof. Allenn C. Lowaton, MSEE
Course Topics:
Introduction to Analog IC Design
MOS transistor biasing and small-signal model
Two-port network analysis
Single stage amplifiers i.e., common-source, common-gate, common-drain
Active loads, current sources and mirrors
MOS capacitances
Frequency response of single stage amplifiers
Differential amplifiers, resistive load, active load and frequency response
Fabrication process
Full Custom IC Design Layout
EDA tools for layout design
Resistors, capacitors and inductors
Bipolar transistors, MOS transistor and logic gates
Design techniques and best practices for layout design
Circuit design and analog block layout design
Device placement and routing
Layout verification and debugging
Course Learning Outcomes:
Design and implement basic analog blocks to build more complex circuits.
Draw the physical layout of a circuit to meet the required specifications such as area, parasitics, and performance.
University Participants—Faculty Trainees (a total of 25)
Caraga State University-Butuan (3)
Caraga State University-Cabadbaran (1)
University of Cebu-Banilad (1)
Bohol Island State University-Main Campus (1)
Notre Dame of Marbel University (1)
Biliran Province State University (2)
MSU-GenSan (2)
Central Philippine University (2)
University of Cebu-LapuLapu and Mandaue (2)
University of Cebu - main campus (1)
University of Cebu-Banilad campus (1)
Mindanao State University-main (2)
Xavier University-Ateneo De Cagayan (2)
Cor Jesu College, Inc (4)
Venue: Virtual/ Remote Access
Course Lecturers:
Dr. Jefferson Hora, PECE
Dr. Gene Fe Palencia
Assoc. Prof. Aileen Gumera
Assoc. Prof. Allenn Lowaton
Asst. Prof. Rochelle Sabarillo
Facilitators:
Kriz Kevin Adrivan (MSEE)
Ritt Vincent Librado (MSEE)
Mark Eric Andam (MSEE)
Johanna Mae Quinalayo (MSEE)
Emrys Oling (BSECE)
Course Topics:
Introduction to Analog IC Design
MOS transistor biasing and small-signal model
Two-port network analysis
Single stage amplifiers i.e., common-source, common-gate, common-drain
Active loads, current sources and mirrors
MOS capacitances
Frequency response of single stage amplifiers
Differential amplifiers, resistive load, active load and frequency response
Fabrication process
Full Custom IC Design Layout
EDA tools for layout design
Resistors, capacitors and inductors
Bipolar transistors, MOS transistor and logic gates
Design techniques and best practices for layout design
Circuit design and analog block layout design
Device placement and routing
Layout verification and debugging
Course Learning Outcomes:
Design and implement basic analog blocks to build more complex circuits.
Draw the physical layout of a circuit to meet the required specifications such as area, parasitics, and performance.
Participants—Trainees
Faculty members of Colegio de Muntinlupa (CDM)
Venue: Microlab Conference Room, MSU-IIT
Course Lecturer:
Nicholas Yee Wee Han, Synopsys Singapore
Course Topics:
1. Introduction
2. Early Design Planning with Black Boxes
3. Multi-Voltage Power Network Design
4. Design Planning with Plan Groups and Voltage Areas; DFA
5. Committing Plan Group to Soft Macros
6. Completing the Block-Level Floorplan and Top-Level Integration
Course Learning Outcomes:
1. Create a hierarchical floorplan of a chip-level design
2. Create TPNS Templates
3. Define TPNS Strategies for top-level rings, as well as a top-level mesh, for a multi-voltage design
4. Use TPNS Template and Strategy to build P/G rings and meshes
5. Analyze the P/G network
6. Push down the P/G network into the soft macros
7. Assign pins on all black boxes
8. Define plan groups for sub-designs
9. Define Voltage Areas
10. Create, shape and place the plan groups and the voltage areas
11. Analyze and improve macro placement using DFA
12. Place pins for best connectivity
13. Derive block-level timing constraints
14. Convert plan groups to soft macros
15. Write floor plans for top and blocks
16. Create a power switch array or ring, and connect the sleep control
17. Modify a “normal” TPNS template to line up with power switches, and make the necessary modifications to the strategies
18. Understand the pros and cons of using DEF vs. Tcl floorplan files for DCT and ICC
19. Re-assemble the top level design with the implemented block level designs
Participants—Trainees
ECE faculty and project researchers of MSU-IIT
Venue: Microlab, MSU-IIT
Course Lecturer:
Nicholas Yee Wee Han, Synopsys Singapore
Course Topics:
1. Synthesis Flow
2. Digital Layout on ICC II
3. Static Timing Analysis on PrimeTime
Course Learning Outcomes:
1. Know the importance of Synthesis in designing Digital IC
2. Input the required Files for Synthesis
3. Know and perform the Synthesis Flow
4. Classify Libraries needed for Synthesis
5. Know the History of Physical Design
6. Know the importance of Place and Route in designing Digital IC
7. Know and perform the Place and Route flow in ICCII
8. Perform Placement, Clock Tree Synthesis, Routing and Chip Finishing
9. Know the importance of Static Timing Analysis in designing Digital IC
10. Explore design clocks
11. Generate and interpret timing reports
12. Generate custom timing information
13. Apply back-annotation files, on-chip variation and additional constraints
University Participants— Faculty Trainees
Ateneo de Davao University
Holy Cross of Davao College
Notre Dame of Marbel University
Notre Dame of Midsayap College
University of Mindanao–Davao
Xavier University
Mindanao State University–Gen. Santos
Caraga State University
Surigao State College of Technology
Universidad de Zamboanga
University of Science and Technology of Southern Philippines
Mindanao State University–Marawi
Venue: Surigao State College of Technology (SSCT), Surigao City
Course Lecturer:
Dr. Xi Zhu, University of Technology Sydney (UTS).
Dr. Jefferson A. Hora, PECE
Engr. Robert Nericua
Engr. Ramon Cristopher Calam
Course Topics:
Hardware Description Language Overview
Introduction to Verilog
Behavioral Modeling
Compiler Directives
Finite State Machine
Course Learning Outcomes:
1. Describe the key features of HDL
2. Differentiate Verilog HDL and VHDL
3. Explain the different levels of abstraction
4. Differentiate the two types of code in most HDL
5. Differentiate Blocking versus Non-blocking Assignment
6. Create a basic building block in Verilog: Module
7. Create a Testbench module
8. Explain combinational logic description in Verilog using behavioral constructs
9. Develop a system for translating FSM state diagrams into Verilog code
10. Understand the design process for implementing a digital design onto FPGA
11. Learn how to use Quartus II to program FPGA
12. Debug a Verilog HDL code
Participants—Trainees
ECE and CpE faculty and students of SSCT
Venue: Microlab, MSU-IIT
Course Lecturer:
Dr. Jefferson A. Hora, PECE
Assoc. Prof. Harreez Villaruz-Quimque, MSEE
Course Topics:
Hardware Description Language Overview
Introduction to Verilog
Behavioral Modeling
Compiler Directives
Finite State Machine
ASIC flow
Chip Design Considerations
Course Learning Outcomes:
1. Describe the key features of HDL.
2. Differentiate Verilog HDL and VHDL.
3. Explain the Digital IC Design Process.
4. Explain the different levels of abstraction.
5. Differentiate the two types of code in most HDL.
6. Differentiate Blocking versus Non-blocking Assignment.
7. Create a basic building block in Verilog: Module.
8. Create a Testbench module.
9. Discuss how to describe a digital circuit using gate-level primitives.
10. Explain combinational logic description in Verilog using behavioral constructs
11. Develop a system for translating FSM state diagrams into Verilog code.
12. Understand the design process for implementing a digital design onto FPGA.
13. Learn how to use Quartus II to program FPGA.
14. Debug a Verilog HDL code.
University Participants—Faculty Trainees
Ateneo de Davao University
Holy Cross of Davao College
Notre Dame of Marbel University
Notre Dame of Midsayap College
Notre Dame of Kidapawan College
Notre Dame University–Cotabato
University of Mindanao–Davao
University of Mindanao–Tagum
Jose Rizal Memorial State University
Camiguin Polytechnic State College
Bukidnon State University
Lyceum of Iligan Foundation
Venue: Microlab, MSU-IIT
Course Lecturer:
Dr. Jefferson A. Hora, PECE
Course Topics:
Analog IC layout components
EDA tools for layout design
Resistors, capacitors and inductors
Bipolar transistors, MOS transistor and logic gates
Design techniques and best practices for layout design
Circuit design and analog block layout design
Device placement and routing
Layout verification and debugging
Course Learning Outcomes:
1. Explain the importance of layout design in the circuit design process.
2. Use layout tool, identity keys and layout basic shapes.
3. Define layers, properties, uses and functions
4. Read and apply design rules to actual layout
5. Describe different types of resistors, capacitors, inductors, diodes, and transistors, their properties, uses and cross sections.
6. Draw layout resistors, capacitor, and transistors given required parameters such as area, resistance, capacitance, inductance, parasitics.
7. Modify layout of resistors, capacitors and transistors base on parameters.
8. Draw layout of different logic gates.
9. Explain the importance of different design techniques and best practices in layout and illustrates them.
10. Identify and explain unwanted effects in a layout design.
11. Draw layout of special protection devices to minimize the occurrences of errors and unwanted effects in the layout
12. Create design placement in a layout and group them according to circuit, functions or common configurations.
13. Describe the different metal layers and VIA connectors and draw their layout
14. Connect devices by wiring using correctly sized metals and VIA connections
15. Create a schematic data, symbols and its equivalent block layout.
16. Explain different verification processes, DRC, LVS, ERC and Antenna.
17. Perform complete verification steps to a given layout.
18. Provide a clean data using layout verification and debugging.
University Participants— Faculty Trainees
Ateneo de Davao University
Holy Cross of Davao College
University of Immaculate Conception
Notre Dame of Midsayap College
Notre Dame University–Cotabato
University of Mindanao–Tagum
Mindanao University of Science and Technology
Venue: Microlab, MSU-IIT
Course Lecturer:
Dr. Jefferson A. Hora, PECE
Dr. Olga Joy Labajo-Gerasta, PECE
Assoc. Prof. Allenn C. Lowaton, MSEE
Engr. Jefrey C. Pasco
Course Topics:
Multi-stage amplifiers
Operational amplifier basics, performance parameters
Miller Two-Stage OTA DC analysis, small signal analysis, frequency response
Feedback circuit analysis, stability analysis
Compensation techniques
Design trade-offs for a compensated Miller OTA
Course Learning Outcomes:
1. Describe the key characteristics of the different types of amplifiers.
2. Explain the limitations of single stage amplifiers and why it is difficult to satisfy the requirements of practical applications.
3. Explain the advantages and disadvantages of using cascade multistage amplifiers.
4. Explain the advantages and disadvantages of using cascode multistage amplifiers.
5. Explain the relationship and effects of amplifier specifications with the circuit design parameters.
6. Simulate and verify the performance of a given operational amplifier.
7. Derive the small-signal two-port network model of a given operational amplifier.
8. Explain the difference between negative and positive feedback circuits and identify applications for such circuits
9. Perform stability analysis for a given negative feedback amplifier circuit.
10. Explain the effects of feedback factor on the stability of negative feedback amplifier circuits.
11. Explain the benefits and cost of applying compensation to feedback amplifier circuits.
12. Apply compensation techniques given an unstable feedback amplifier circuit.
13. Describe the effects of compensation to time and frequency response of a given amplifier in feedback.
14. Design a two-stage Miller OTA systematically to satisfy given specifications and highlight design trade-offs.
University Participants— Faculty Trainees
Ateneo de Davao University
Jose Rizal Memorial State University
La Salle University–Ozamis
Mindanao University of Science and Technology
Notre Dame of Midsayap College
University of Mindanao–Davao City
Xavier University
Venue: Microlab, MSU-IIT
Course Lecturer:
Dr. Jefferson A. Hora, PECE
Dr. Olga Joy Labajo-Gerasta, PECE
Assoc. Prof. Allenn C. Lowaton, MSEE
Engr. Jefrey C. Pasco
Course Topics:
MOS transistor biasing and small-signal model
Two-port network analysis
Single stage amplifiers i.e. common-source, common-gate, common-drain
Active loads, current sources and mirrors
MOS capacitances
Frequency response of single stage amplifiers
Differential amplifiers, resistive load, active load and frequency response
Fabrication process
Course Learning Outcomes:
1. Describe the regions of operation of a MOS transistor
2. Describe the conditions to bias a MOS transistor in a desired region
3. State and explain the factors affecting the drain current of a transistor
4. Describe the non-idealities and short-channel effects on the operation of the MOS transistor
5. Explain the importance of small-signal modelling of the transistor
6. Illustrate and describe mathematically the small-signal model of a transistor
7. Describe how the small-signal parameters vary with the operating region
8. Obtain the required size and bias of a transistor to achieve a target transconductance or output impedance
9. Describe the three basic single stage amplifier topologies i.e. common-source, common-gate, common-drain
10. Derive and simulate the equivalent two-port network parameters of single stage amplifiers
11. Obtain the size of single stage amplifiers to achieve required performance
12. State the advantages and disadvantages of using active loads compared with using resistive-loads for single stage amplifiers
13. Describe the bias conditions required for a transistor active load and current mirrors
14. Obtain the size of a transistor active load to achieve required amplifier performance
15. Describe the components of the parasitic capacitances in a MOS transistor
16. Describe the effects of MOS parasitic capacitances in single stage amplifiers frequency response
17. Derive the frequency response of single stage amplifiers
18. Describe how the frequency response is affected by the amplifier parameters
19. State the advantages of using differential signals over single-ended signals
20. Describe the differences between differential amplifiers with resistive loads and active loads
21. Obtain the size of transistors of a differential amplifier to achieve required performance
22. Describe and derive the frequency response of differential amplifiers.
University Participants— Faculty Trainees
Agusan del Sur State College of Agriculture and Technology –Bunawan, Agusan del Sur
Caraga State University–Butuan City
Jose Rizal Memorial State University
La Salle University–Ozamis
Mindanao University of Science and Technology
Notre Dame of Midsayap College
Notre Dame University–Cotabato
Xavier University
Venue: Old Microlab, COE Bldg., MSU-IIT
Course Trainer:
Dr. Jefferson A. Hora, PECE
Assoc. Prof. Harreez M. Villaruz
Course Topics:
Introduction to Verilog HDL (Gate level and RTL Abstraction.
Introduction to Altera–Quartus tool
Familiarization of Altera FPGA board
Hand-on design verification with FPGA board with the following design exercises:
Up/down counter
Hit the mouse
Vending machine
University Participants— FacultyTrainees
Notre Dame University—Cotabato City
La Salle University—Ozamis City
MSU-Iligan Institute of Technology (MSU-IIT)
Venue: CFSS Open Lab, COE Bldg., MSU-IIT
Synopsys Course Trainer:
Yeong Bin Lee
Course Topics:
Custom design verification (DRC and LVS) through Hercules tools.
Parasitic Extraction and Analysis through StarRC tools.
University Participants—Trainees (Faculty and RAs)
MSU-Iligan Institute of Technology (MSU-IIT)
University of the Philippines-Diliman (UPD)
De La Salle University (DLSU-Taft)
Ateneo de Manila University (ADMU)
Mapua University (MIT)
University of San Carlos (USC)
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