Advancing Philippine Microelectronics: The 2026 Voltage Reference Design and SAR ADC IC Design Training

The 2026 Voltage Reference Design Methodology with SAR ADC IC Design Training was successfully convened from August 13 to August 15, 2026, at the Camiguin Polytechnic State College (CPSC) campus. Formally titled "From Reference to Resolution: A Hands-on Training Workshop on Voltage References and SAR ADCs" under the IECEP-IBC Technical Training Workshop series, this intensive three-day program was spearheaded by Dr. Jefferson A. Hora, Director of the Center for Integrated Circuits Design (CICD) and Dean of the MSU-IIT College of Engineering.

Supported by the Department of Science and Technology – Philippine Council for Industry, Energy and Emerging Technology Research and Development (DOST-PCIEERD) under the CHIP IP Block Program, the initiative aims to strengthen regional technical capacity, elevate specialized expertise, and democratize access to high-tier semiconductor education across Mindanao and the broader Philippine engineering landscape.

Program Highlights and Collaborative Vision

The opening ceremonies set a foundational and inspiring tone, bringing together academic leaders, researchers, and prominent industry partners. Following welcome remarks by Dr. Jefferson A. Hora, Dr. Maria Louella Salcedo, Director for Research Development and Innovation, delivered a special message emphasizing cross-institutional collaboration as a vital pillar for technological progress.

The program was significantly bolstered by industry sponsorship from Tekmark, highlighting a shared commitment between academia and private sectors. Engr. Luwell Balagas, Solutions Engineer at Tekmark, delivered a featured talk on "Semiconductor/IC Solutions in Research and Training," focusing on modern test instruments and EDA solutions crucial for advanced microelectronics workflows.

Core Technical Tracks and Hands-On Labs

The training combined rigorous theoretical frameworks with immersive, industry-grade computer-aided design (CAD) simulations using tools like Cadence Virtuoso:

• Day 1: MOSFET-Based Voltage Reference Design — Assoc. Prof. Nieva Mapula led sessions unpacking the fundamentals of CMOS voltage references, semiconductor thermal physics, bandgap architectures, temperature compensation techniques, and reference buffer design for rapid settling.

• Day 2: Successive Approximation Register (SAR) ADC Architectures — Assoc. Prof. Allenn C. Lowaton covered analog-to-digital conversion principles, binary search mechanics, capacitive DAC structures, and static/dynamic performance metrics such as INL, DNL, and ENOB. Participants also undertook their first major laboratory module on designing and optimizing CMOS voltage reference circuits.

• Day 3: Full Mixed-Signal System Integration — Concluding the technical program, attendees integrated standalone voltage reference blocks with full 8-bit capacitive SAR ADC modules, performing comprehensive mixed-signal transient simulations to validate digital output codes and system linearity.

Expanding Regional Innovation and Future Outlook

By decentralizing integrated circuit design training from major metropolitan hubs to regional institutions like CPSC, the initiative successfully bridged educational gaps and provided high-value technical training to engineering faculty and students from diverse universities across Visayas and Mindanao.

The workshop concluded with a formal closing ceremony celebrating the achievements of all participants and facilitators. By fostering localized expertise in reusable IP block development, programs like the CICD CHIP IP Block Initiative continue to lay a robust, scalable foundation for the Philippines' burgeoning role in the global semiconductor supply chain.