• Emrys Leowhel Oling, Jess mart Anticamara & Ina Coleen Canto "A Low Noise, Capacitorless Low Dropout Regulator Using A 65 nm Technology"

• Ritt Vincent A. Librado & Andrew Phillip B. Olaivar "Operational Transconductance Amplifier Design for MEMS Accelerometer Application in TSMC 65nm Technology Process"

• Patrick Dale G. Cuartero  "Design and Implementation of Scalable Universal Matrix Multiplication Algorithm on Field Programmable Gate Array"

•  Khryzel  Mae P.  Tan "A Low-Noise Figure High- Conversion Gain Down-Conversion Mixer in 65NM CMOS Process"

• Mae B. Dedoro & Clandine L. Salvedia "Dynamic Charge Transfer Switch (CTS) Charge Pump for Flash Memories in 65nm CMOS Technology"

• Patrick P. De Claro, Mohammed G. Masahud & Jamalicah A. Nagamora "Development of a Microprocessor Core Based on Amber 23 Processor Core Architecture"

•  Jamil Francis B. Cuadra & Honey Fatima R. Velasco "Implementation Of Double-Tail Dynamic Latch Comparator And 3-Split Capacitor Array DAC In 12-Bit Successive Approximation Register Analog-To-Digital Converter"

• Aldrei Zamm D. Recamadas & Raymond Jade R. Silvosa "Low Input Voltage Charge Pump for Thermoelectric Energy Harvesting Interface Circuit in 65nm CMOS Technology"

• George C. Omongos & Nicole A. Tabaculde "Hybrid Multistage Differential Rectifier for Indoor Light Energy Harvester in 65nm CMOS Technology"

• Mark Lester M. Acodili "A Differential Ring Oscillator for Wireless Sensor Network Applications Implemented in 65nm CMOS Technology Process"

• Gregel G. Redublado Jr. & Jessef Audrey M. Barosa "Implementation of 1.5x and 2x Overstress-Free Series-Parallel Switched-Capacitor DC-DC Converters and its Limitations in 65nm CMOS Technology Process"

• John Xavier Toledo "1.2V Nanowatts gm/Id-based Subthreshold Operational Amplifier Using Cascode-Lee Load Combination Architecture for Bandgap Voltage Refrence in 65nm CMOS Process"

• Dinah Pearl S. Madelo &  Angeline G. Tayros "A Comparative Study on P-Gated Schmitt Trigger SRAM and Standard  Cell Asic Memory Array in 65nm CMOS Technology"

• Lemuel Fil L. Bañez "ESD Protection Circuit for V-Band RF Applications in A 65-nm CMOS Technology"

• Elaine Grace O. Tabacon "2.4 GHz ISM Band Application Low Noise Amplifier with Active Inductor Load Implemented in 65nm CMOS Process"

• Miracel June G. Cesar & Jan Marie B. Yting "A 10-MHz Refence Clock Phase Locked Loop Frequency Synthesizer with Differential Charge Pump and Phase Frequency Detector Using GDI Technique"

• Jonalyn N. Gabutan "Low Power Four Phase Voltage Multiplier with Differential Self-Vth Cancellation Scheme and Tri-Charge Sharing Clock Scheme"

• Sushima May M. Imperial & Jordan M. Juanday "10-Bit Low Power Successive  Approximation Register ADC for Wireless Sensor Networks"

• Marc Stephen Abellana & Ezra Christine Ypil "A High PSRR LDO Based on Feed Forward Ripple Cancellation Technique Implemented in 65nm Technology"

• Renee Anne Albarracin & Rafael Gamo "Delay-Locked Loop with Start-Controlled Phase-Frequency Detector"

• Kriz Kevin C. Adrivan & Harris W. Guinomla "Wifi Energy Harvester with Charge Control Mechanism "

• Kenneth Bryan Dagasdas & Dean Jeremy Dagting "FPGA Based Wireless Heart Rate and Body Temperature Measuring System'

• Mark Eric C. Andam & Charlene Mae P. Canja "A Design of Self-Biased Cross Cuopled Rectifier with Integrated Dual Threshold Voltage for RF Energy Harvesting Application"

• Garyl Jay N. Pepito "CMOS RC Oscillator for Microcontroller Applications with Current Trimming Approach"

• Mohamad Fahad Cader & Kenneth Kyle Diez "Low Power Design of 4-KB SRAM Implemented in 65nm Technology "

• Dave Darryl Ditucalan "A gm/Id-based Subthreshold Operation Amplifier with Current Subtractor Adaptive Biasing Circuit"

• Niña Kirstin L. Pacamalan & Kenneth John P. Ibarra "Design of Pulse Width Modulation/Pulse Frequency Modulation Mode for a Buck Converter in 65nm CMOS Process"

• Kathleen Kaye  Alcuizar & Robert Leemar M. Bagundol "Design of Delay  Line Time to Digital Converter Based Temperature Sensor"

• Blesshe Mae Beron & Varrie Duhaylungsod "Design of High Throughput and Low Power Cryptographic Core using Blowfish Algorithm"

 ⭐ BEST PAPER in IEEE HNICEM 2019

• Dessa Piandong  "CMOS Implemented Trans Impedance Amplifier for Optical Communications"

• Krisha Dawn Dura & Chrizia Mae Nabua  "Monolithic Microwave Integrated Circuit (MMIC) Design of Inverse Class-J Power Amplifier with Varactor Diode for High Efficiency in 4G Communications System"

•  Daryl S. Auguis "Gs/s Track-and Hold- Circuit in 90nm CMOS Process Technology"

•  Lovely Jane V. Vallinas "Design of a Low-Power Internal Receiver Front-End Circuit for Wireless Downlink in Neural Prosthesis Implantable Medical Device"

• John Ray Chan "Low Power Boost Converter for Pacemaker Energy Harvesting Application  "

• Camsia Minaga "Low Dropout Voltage Regulator for Vivo Biomedical Implantable Devices Implemented in 90nm CMOS Process Technology"

• Rhea Vanessa Acut & Sushimae Nabangue "Comparison Between 90nm and 32nm CMOS Technology Implementation of Low Voltage Bandgap Reference with PSR Enhancement Stage"

• Darwen Corgue  & Kevin Maglinte "Filterless Class-D Amplifier"

• Meilyssa A. Mayormita & John Raul C. Rebollos  "On-Chip Indoor Light Energy Harvester for Ultra-Low-Power Applications Implemented in 90nm CMOS Process Technology "

• Marnier B. Bate & Emmanuel D. Talagon "RF-to-DC Converter for Ultra-low Power Application"

• Gil Michael E. Regalado "Integration Of OpenCV And Cyclone V Hybrid ARM and FPGA SoC for Face Detection Application"

• Larry Gerard G. Aquino & Leocarl M. Viñalon "A 500 MHz Fast-Locking Delay-Locked Loop with Linear Delay Element"

• Kento A. Fujimori & Keno Arnieldo T. Hibaya  "On-Chip CMOS Multi-Band Matching Circuit for RF Energy Harvesting"

• Muhammad Shaheed D. Ibrahim & Mohammad Ali M. Muti "AM Transmitter Implemented in 0.18µm CMOS Process Technology'

• Dominic O. Cagadas "18-bit Decimator Design for Sigma-Delta ADC with Variable Oversampling Rate for Audio Application"

• Jebien May Calapiz "3rd, 4th & 5th Order Single-Stage Delta-Sigma Modulator for an 18-Bit Audio DAC"

• Christina A. Garcia & Stella Sofia I. Sabate "A 1.8V 640-MHz Phase Locked Loop as a Frequency Multiplier for Continuous-time Sigma-Delta ADC"

• Vincent Heramiz & Pleiades Longkit "A 1 GHz Delay-Locked Loop Using a 4-Cell Delay-Time with Extended Inverters"

• Kresil Joy Jimenez & Cris Tero "A Design for High Speed CMOS Fully Parallel Content-Addressable Memory"

• Meliza C. Capino & Lyneth N. Rivera "Closed Loop Fractional Step-Down Charge Pump DC-DC Converter with Digital Control Design"

• Ultraviolet R. Morandante & Jourdan A. Mabayo "High Efficiency Power Converter for RFID Application"

• Roberto Madronial, Jr. & Daryl Pongcol "Implementation of the Hard-Decision Algorithm Low-Density Parity Check Codes in a 0.13µm CMOS Process"

• Kramer C. Chua & Demie mae V. Dajao "Design and Implementation of Universal Synchronous Asynchronous receiver Transmitter on Verilog HDL"

• Meynard Hamak & Aaron Kris Suizo "PWM Boost Converter for Multi-Channel Constant-Current LED Driver"

• Marjulyn Doce, Isovelle Lanz Embalsado, Loie Adrian Fernandez & Alpe John Santos "12-Bit Cascaded-Folding and Cascaded-Interpolating in 90nm CMOS Technology" 

• John David Mangali & Kenneth Harvey Duque "2-1, 2-2 And 2-1-1 Mash Modulators for 18bit Audio DAC"        

• John Ray Esic & Van Louven Buot "Step-Down DC-DC Converter Charge Pump with Digital Control in 90nm CMOS Process Technology"   

• Jimmy  Colaste & Jennifer Ian Ligtao  "Protection Circuits (OTP,OCP & OVP) Design in 90nm CMOS Process Technology for DC-DC Converter"      

• Saidaliah Sarip & Quenie Alico "125 MHz 16 X 16 SROM via Cell-Based"

• Jayson Loreto, Sheerah Dale Orlasan, Lavern Bete & Honey Mae Tagalogon "12-Bit Pipeline ADC-Implemented in 0.09-um Digital CMOS Technology for Powerline Alliance"  

• Jenelyn Tiwanac &Rochelle Sabarillo "Step-Down Charge Pump Design in 90nm CMOS Process with Enhance Voltage Regulation"         

• Michelle Batu & Danielene Caberte "10-bit High Resolution DAC with Fully Segmented Dynamic Element Matching"

• Franzymell Dy & Renato Bringas, Jr. "10-Bit Segmented Current-Steering DAC in CMOS 90nm Process"

• Leo Geralla & Kimberly Mae Bayang "6-bit Flash ADC Using Interpolating Technique Implemented in 90nm CMOS Process"   

• Lester Jandraux  Gabrillo & Mark Geoffray Gales "Enhanced RF to DC Converter with LC Resonant Circuit"

• Aprilyne Tiongson & Gino Gupana "High Speed Optical Receiver Front-End Implemented in 90nm CMOS Technology"

• AArthur Garao & Ronnie Asino "1.2v, 3.3v 8-bit Sub-Ranging Flash ADC Using Pseudo-Dynamic with 1-GHz Clock Frequency"

• Ace John Tiongco & Jeffrey Armingol "10-bit 90nm CMOS SAR ADC"                

• Mark Cyril Jubay  "Full Custom Design of Split-Set Data Weighted Averaging for 3 bit Unit Elements Digital-Analog Converter"

• Keith Francisco "Low Voltage Bandgap Reference With PSR Enhancement Stage Implemented in 90nm CMOS Technology"

⭐ Best College Thesis

• Christine Mendoza & Oscar Balatero "Digital Implementation Of A 3-bit Digital-To-Analog Converter With Dynamic Element Matching Using Data Weighted Averaging For Linearity Enhancement"

• Richmod Magallon & Chenny Caberteja "PWM Controlled Buck Converter For Multi-Channel Constant-Current LED Driver"

• Kent Dun Lagaras "Different Digital Cancellation Logic (DCL) Design For Multistage Noise Shaping (MASH) 2.2/2.1/1.1 Analog-To-Digital (A/D) Converter"

• Jameen Macabanding  "Comparison Between The Stability And Over-all Performance Of A Type II And Type III Compensation Network In A PWM Boost Converter"       

• Mohammad Hudhaif Bin Shedique Alug  "Two-Level Flash Time-To-Digital Converter For Period Measurement"      

•   Geo Macana & Jexter Babatugon "Voltage-Mode Synchronous PWM/PFM Buck Converter"

• Meynard Hamak & Kris Suizo Aaron "Multi-Channel Constant-Current Led Driver With Boost Converter"        

• Tarhata Sandra Badelles, Gideon John Paza, & Kathy Venzon "18-Bit Audio Mash 2-2 Sigma Delta ADC"

• Jessica Aileen Aldueso, Darwin Mangca, Cris Nickson Aleman, & Michael Vincent Mosquera "18-Bit Delta-Sigma D/A Converter –5th Order Cascoded Modulator Architecture "

• Mycel Capilayan, Mark Laurence Dandan, & Sittie Aleyah Magayo-Ong "3rd – Order Dual Truncation 18-Bit Audio Mash 2-1 Delta-Sigma DAC in 90nm CMOS Technology Implementation"  

• Daisy Caas &Yitzhak Huevos "8-Bit DAC for Zilog Z8 Encore ADC "        

• Jose Ricardo Catane & Mark Jayson Mortel "8-Bit DAC With Partial Randomization Dynamic Element Matching  for Nonlinear Distortion Correction"

• Frandee Von Del Socorro "Power Efficiency Class D Amplifier"      

• Isaac Sammuel Arancon "Low Dropout Voltage Regulator Design In 90nm CMOS Technology Process"     

• Jefferson Piscos "Low Power, Low Voltage Bandgap Reference Circuit in 90nm CMOS Technology Process"

• Kyle Kester Bahian, Lucernas & Ruby Ann Sabugal "Modulator Design of an 18-Bit 3rd Order (2-1 MASH) Sigma-Delta ADC In 90nm CMOS Process"

• Natasha Mae Jao "Over-Current Protection Circuit for Buck DC-DC Converter Design in 90nm CMOS Technology Process"

•  Emerson Santiago "PFM Controller Design in 90nm CMOS Process"

• Adren Cartajenas "Pulse Width Modulation Controller For DC-DC Converter Implemented in 90nm CMOS Technology Process" 

• Marl Hussein Niñal "Type III Compensator for Synchronous DC-DC Buck Converter using 90nm Process"          

• Aebeedec Jan Luciano "Ultra-Low-Power Digitally-Controlled Oscillator For ADPLL For SOC Applications Described In Verilog HDL"