• SoC Design Planning Integration

Date: April 15-17, 2019.

Venue: Microlab Conference Room, MSU-IIT

Course Lecturer: Nicholas Yee Wee Han, Synopsys Singapore

Topics: 

1. Introduction

2. Early Design Planning with Black Boxes

3. Multi-Voltage Power Network Design

4. Design Planning with Plan Groups and Voltage Areas;  DFA

5. Committing Plan Group to Soft Macros

6. Completing the Block-Level Floorplan and Top-Level Integration

Course Learning Outcomes:

1. Create a hierarchical floorplan of a chip-level design

2. Create TPNS Templates

3. Define TPNS Strategies for top-level rings, as well as a top-level mesh, for a multi-voltage design

4. Use TPNS Template and Strategy to build P/G rings and meshes

5. Analyze the P/G network

6. Push down the P/G network into the soft macros

7. Assign pins on all black boxes

8. Define plan groups for sub-designs

9. Define Voltage Areas

10. Create, shape and place the plan groups and the voltage areas

11. Analyze and improve macro placement using DFA

12. Place pins for best connectivity

13. Derive block-level timing constraints

14. Convert plan groups to soft macros

15. Write floor plans for top and blocks

16. Create a power switch array or ring, and connect the sleep control

17. Modify a “normal” TPNS template to line up with power switches, and make the necessary modifications to the strategies

18. Understand the pros and cons of using DEF vs. Tcl floorplan files for DCT and ICC

19. Re-assemble the top level design with the implemented block level designs

Participants—Trainees

• ECE faculty and project researchers of MSU-IIT