Trainings and Extension Activities
- Introduction to HDL with FPGA
Date: April 24-28, 2019.
Venue: Surigao State College of Technology (SSCT), Surigao City
•Dr. Xi Zhu, University of Technology Sydney (UTS).
•Dr. Jefferson A. Hora, PECE
•Engr. Robert Nericua
•Engr. Ramon Cristopher Calam
Hardware Description Language Overview
Introduction to Verilog
Finite State Machine
Course Learning Outcomes:
1. Describe the key features of HDL
2. Differentiate Verilog HDL and VHDL
3. Explain the different levels of abstraction
4. Differentiate the two types of code in most HDL
5. Differentiate Blocking versus Non-blocking Assignment
6. Create a basic building block in Verilog: Module
7. Create a Testbench module
8. Explain combinational logic description in Verilog using behavioral constructs
9. Develop a system for translating FSM state diagrams into Verilog code
10. Understand the design process for implementing a digital design onto FPGA
11. Learn how to use Quartus II to program FPGA
12. Debug a Verilog HDL code
ECE and CpE faculty and students of SSCT.
2/F Room 209C, College of Engineering and Technology, MSU-Iligan Institute of Technology,
Andres Bonifacio Ave., Tibanga, Iligan City, 9200, Philippines
T: (+63) 221 - 4050 loc. 4652 or (+63) 221 - 4050 local 4131
GRADUATE (BS/MS) ALUMNI SURVEY
To all BSECE and MSEE (Microelectronics) graduates of MSU-IIT: We humbly request few minutes of your time to answer this short survey. This will help us to continuously improve our BSECE (Microelectronics Track) and MSEE in Microelectronics program. Thank you very much!