Trainings and Extension Activities

  • Introduction to HDL with ASIC IC Design Flow and FPGA

Date: November 6-10, 2017.

Venue: Microlab, MSU-IIT

Course Lecturer:

Dr. Jefferson A. Hora, PECE

•Assoc. Prof. Harreez Villaruz-Quimque, MSEE

Topics:

  1. Hardware Description Language Overview

  2. Introduction to Verilog

  3. Behavioral Modeling

  4. Compiler Directives

  5. Finite State Machine

  6. ASIC flow

  7. Chip Design Considerations

Course Learning Outcomes:

1. Describe the key features of HDL.

2. Differentiate Verilog HDL and VHDL.

3. Explain the Digital IC Design Process.

4. Explain the different levels of abstraction.

5. Differentiate the two types of code in most HDL.

6. Differentiate Blocking versus Non-blocking Assignment.

7. Create a basic building block in Verilog: Module.

8. Create a Testbench module.

9. Discuss how to describe a digital circuit using gate-level primitives.

10. Explain combinational logic description in Verilog using behavioral constructs

11. Develop a system for translating FSM state diagrams into Verilog code.

12. Understand the design process for implementing a digital design onto FPGA.

13. Learn how to use Quartus II to program FPGA.

14. Debug a Verilog HDL code.


University Participants—Faculty Trainees

  1. Ateneo de Davao University

  2. Holy Cross of Davao College

  3. Notre Dame of Marbel University

  4. Notre Dame of Midsayap College

  5. Notre Dame of Kidapawan College

  6. Notre Dame University–Cotabato

  7. University of Mindanao–Davao

  8. University of Mindanao–Tagum

  9. Jose Rizal Memorial State University

  10. Camiguin Polytechnic State College

  11. Bukidnon State University

  12. Lyceum of Iligan Foundation

Click here for details: (report, news, photos)

jayrold_training_FPGA.mp4

CONTACT INFORMATION:


2/F Room 209C, College of Engineering and Technology, MSU-Iligan Institute of Technology,

Andres Bonifacio Ave., Tibanga, Iligan City, 9200, Philippines

T: (+63) 221 - 4050 loc. 4652 or (+63) 221 - 4050 local 4131





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