Trainings and Extension Activities

Date: November 6-10, 2017.

Venue: Microlab, MSU-IIT

Course Lecturer: 

Dr. Jefferson A. Hora, PECE

•Assoc. Prof. Harreez Villaruz-Quimque, MSEE


Course Learning Outcomes:

1. Describe the key features of HDL.

2. Differentiate Verilog HDL and VHDL.

3. Explain the Digital IC Design Process.

4. Explain the different levels of abstraction.

5. Differentiate the two types of code in most HDL.

6. Differentiate Blocking versus Non-blocking Assignment.

7. Create a basic building block in Verilog: Module.

8. Create a Testbench module.

9. Discuss how to describe a digital circuit using gate-level primitives.

10. Explain combinational logic description in Verilog using behavioral constructs

11. Develop a system for translating FSM state diagrams into Verilog code.

12. Understand the design process for implementing a digital design onto FPGA.

13. Learn how to use Quartus II to program FPGA.

14. Debug a Verilog HDL code.

University Participants—Faculty Trainees

Click here for details: (report, news, photos, SO)



2/F  Room 209C,                                        College of Engineering and Technology, MSU-Iligan Institute of Technology, 

Andres Bonifacio Ave., Tibanga,        Iligan City, 9200, Philippines    

T: (+63) 221 - 4050 loc. 4652 or              (+63) 221 - 4050 local 4131


To all BSECE and MSEE (Microelectronics) graduates of MSU-IIT: We humbly request few minutes of your time to answer this short survey. This will help us to continuously improve our BSECE (Microelectronics Track) and MSEE in Microelectronics program. Thank you very much!