Trainings and Extension Activities
- Front and Back-end Full Custom IC Design
(1-month Virtual/Remote Training for Collegio de Muntinlupa College)
Date: July 2-29, 2022
Venue: Virtual
Course Lecturers:
Dr. Jefferson Hora, PECE
Dr. Gene Fe Palencia
Assoc. Prof. Aileen Gumera
Assoc. Prof. Allenn Lowaton
Asst. Prof. Rochelle Sabarillo
Facilitators:
Kriz Kevin Adrivan (MSEE)
Ritt Vincent Librado (MSEE)
Mark Eric Andam (MSEE)
Johanna Mae Quinalayo (MSEE)
Emrys Oling (BSECE)
Topics:
Introduction to Analog IC Design
MOS transistor biasing and small-signal model
Two-port network analysis
Single stage amplifiers i.e., common-source, common-gate, common-drain
Active loads, current sources and mirrors
MOS capacitances
Frequency response of single stage amplifiers
Differential amplifiers, resistive load, active load and frequency response
Fabrication process
Full Custom IC Design Layout
EDA tools for layout design
Resistors, capacitors and inductors
Bipolar transistors, MOS transistor and logic gates
Design techniques and best practices for layout design
Circuit design and analog block layout design
Device placement and routing
Layout verification and debugging
Course Learning Outcomes:
Design and implement basic analog blocks to build more complex circuits.
Draw the physical layout of a circuit to meet the required specifications such as area, parasitics, and performance.
Participants—Trainees
Faculty members of Colegio de Muntinlupa (CDM)
CONTACT INFORMATION:
2/F Room 209C, College of Engineering and Technology, MSU-Iligan Institute of Technology,
Andres Bonifacio Ave., Tibanga, Iligan City, 9200, Philippines
T: (+63) 221 - 4050 loc. 4652 or (+63) 221 - 4050 local 4131
GRADUATE (BS/MS) ALUMNI SURVEY
To all BSECE and MSEE (Microelectronics) graduates of MSU-IIT: We humbly request few minutes of your time to answer this short survey. This will help us to continuously improve our BSECE (Microelectronics Track) and MSEE in Microelectronics program. Thank you very much!
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