Trainings and Extension Activities

  • FPGA—IC Design Verification

Date: April 10-13, 2012

Venue: Old Microlab, COE Bldg., MSU-IIT

Course Trainer:

◘ Dr. Jefferson A. Hora, PECE

◘ Assoc. Prof. Harreez M. Villaruz


  1. Introduction to Verilog HDL (Gate level and RTL Abstraction.

  2. Introduction to Altera–Quartus tool

  3. Familiarization of Altera FPGA board

  4. Hand-on design verification with FPGA board with the following design exercises:

○ up/down counter

○ hit the mouse

○ vending machine

University Participants— FacultyTrainees

  1. Notre Dame University—Cotabato City

  2. La Salle University—Ozamis City

  3. MSU-Iligan Institute of Technology (MSU-IIT)

Click here for details: (documents)


2/F Room 209C, College of Engineering and Technology, MSU-Iligan Institute of Technology,

Andres Bonifacio Ave., Tibanga, Iligan City, 9200, Philippines

T: (+63) 221 - 4050 loc. 4652 or (+63) 221 - 4050 local 4131


To all BSECE and MSEE (Microelectronics) graduates of MSU-IIT: We humbly request few minutes of your time to answer this short survey. This will help us to continuously improve our BSECE (Microelectronics Track) and MSEE in Microelectronics program. Thank you very much!