Trainings and Extension Activities
- FPGA—IC Design Verification
Date: April 10-13, 2012
Venue: Old Microlab, COE Bldg., MSU-IIT
Course Trainer:
◘ Dr. Jefferson A. Hora, PECE
◘ Assoc. Prof. Harreez M. Villaruz
Topics:
Introduction to Verilog HDL (Gate level and RTL Abstraction.
Introduction to Altera–Quartus tool
Familiarization of Altera FPGA board
Hand-on design verification with FPGA board with the following design exercises:
○ up/down counter
○ hit the mouse
○ vending machine
University Participants— FacultyTrainees
Notre Dame University—Cotabato City
La Salle University—Ozamis City
MSU-Iligan Institute of Technology (MSU-IIT)
CONTACT INFORMATION:
2/F Room 209C, College of Engineering and Technology, MSU-Iligan Institute of Technology,
Andres Bonifacio Ave., Tibanga, Iligan City, 9200, Philippines
T: (+63) 221 - 4050 loc. 4652 or (+63) 221 - 4050 local 4131
GRADUATE (BS/MS) ALUMNI SURVEY
To all BSECE and MSEE (Microelectronics) graduates of MSU-IIT: We humbly request few minutes of your time to answer this short survey. This will help us to continuously improve our BSECE (Microelectronics Track) and MSEE in Microelectronics program. Thank you very much!
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