Trainings and Extension Activities
- Cloud-based Synthesis Using Design Compiler
Date: April 8-13, 2019.
Venue: Microlab, MSU-IIT
Course Lecturer: Nicholas Yee Wee Han, Synopsys Singapore
Topics:
1. Synthesis Flow
2. Digital Layout on ICC II
3. Static Timing Analysis on PrimeTime
Course Learning Outcomes:
1. Know the importance of Synthesis in designing Digital IC
2. Input the required Files for Synthesis
3. Know and perform the Synthesis Flow
4. Classify Libraries needed for Synthesis
5. Know the History of Physical Design
6. Know the importance of Place and Route in designing Digital IC
7. Know and perform the Place and Route flow in ICCII
8. Perform Placement, Clock Tree Synthesis, Routing and Chip Finishing
9. Know the importance of Static Timing Analysis in designing Digital IC
10. Explore design clocks
11. Generate and interpret timing reports
12. Generate custom timing information
13. Apply back-annotation files, on-chip variation and additional constraints
University Participants— Faculty Trainees
Ateneo de Davao University
Holy Cross of Davao College
Notre Dame of Marbel University
Notre Dame of Midsayap College
University of Mindanao–Davao
Xavier University
Mindanao State University–Gen. Santos
Caraga State University
Surigao State College of Technology
Universidad de Zamboanga
University of Science and Technology of Southern Philippines
Mindanao State University–Marawi
CONTACT INFORMATION:
2/F Room 209C, College of Engineering and Technology, MSU-Iligan Institute of Technology,
Andres Bonifacio Ave., Tibanga, Iligan City, 9200, Philippines
T: (+63) 221 - 4050 loc. 4652 or (+63) 221 - 4050 local 4131
GRADUATE (BS/MS) ALUMNI SURVEY
To all BSECE and MSEE (Microelectronics) graduates of MSU-IIT: We humbly request few minutes of your time to answer this short survey. This will help us to continuously improve our BSECE (Microelectronics Track) and MSEE in Microelectronics program. Thank you very much!
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