Undergraduate (BS ECE) Thesis/IC Designs

AY 2020-2021

• A Low Noise, Capacitorless Low Dropout Regulator Using A 65 nm Technology

Author : Emrys Leowhel Oling, Jess mart Anticamara & Ina Coleen Canto

AY 2018-2019

• Operational Transconductance Amplifier Design for MEMS Accelerometer Application in TSMC 65nm Technology Process

Author : Ritt Vincent A. Librado & Andrew Phillip B. Olaivar

AY 2017-2018

• Design and Implementation of Scalable Universal Matrix Multiplication Algorithm on Field Programmable Gate Array .

Author: Patrick Dale G. Cuartero

• A Low-Noise Figure High- Conversion Gain Down-Conversion Mixer in 65NM CMOS Process.

Author: Khryzel Mae P. Tan

• Dynamic Charge Transfer Switch (CTS) Charge Pump for Flash Memories in 65nm CMOS Technology.

Authors: Mae B. Dedoro, and Clandine L. Salvedia

AY 2016-2017

• Development of a Microprocessor Core Based on Amber 23 Processor Core Architecture.

Authors: Patrick P. De Claro, Mohammed G. Masahud, and Jamalicah A. Nagamora

• Implementation Of Double-Tail Dynamic Latch Comparator And 3-Split Capacitor Array DAC In 12-Bit Successive Approximation Register Analog-To-Digital Converter.

Authors: Jamil Francis B. Cuadra, and Honey Fatima R. Velasco

• Low Input Voltage Charge Pump for Thermoelectric Energy Harvesting Interface Circuit in 65nm CMOS Technology.

Authors: Aldrei Zamm D. Recamadas, and Raymond Jade R. Silvosa

• Hybrid Multistage Differential Rectifier for Indoor Light Energy Harvester in 65nm CMOS Technology.

Authors: George C. Omongos, and Nicole A. Tabaculde

• A Differential Ring Oscillator for Wireless Sensor Network Applications Implemented in 65nm CMOS Technology Process.

Authors: Mark Lester M. Acodili

• Implementation of 1.5x and 2x Overstress-Free Series-Parallel Switched-Capacitor DC-DC Converters and its Limitations in 65nm CMOS Technology Process.

Authors: Gregel G. Redublado Jr., and Jessef Audrey M. Barosa

• 1.2V Nanowatts gm/Id-based Subthreshold Operational Amplifier Using Cascode-Lee Load Combination Architecture for Bandgap Voltage Refrence in 65nm CMOS Process.

Author: John Xavier Toledo

• A Comparative Study on P-Gated Schmitt Trigger SRAM and Standard Cell Asic Memory Array in 65nm CMOS Technology.

Authors: Dinah Pearl S. Madelo, and Angeline G. Tayros

• ESD Protection Circuit for V-Band RF Applications in A 65-nm CMOS Technology.

Author: Lemuel Fil L. Bañez

• 2.4 GHz ISM Band Application Low Noise Amplifier with Active Inductor Load Implemented in 65nm CMOS Process.

Author: Elaine Grace O. Tabacon

• A 10-MHz Refence Clock Phase Locked Loop Frequency Synthesizer with Differential Charge Pump and Phase Frequency Detector Using GDI Technique.

Authors: Miracel June G. Cesar and Jan Marie B. Yting

• Low Power Four Phase Voltage Multiplier with Differential Self-Vth Cancellation Scheme and Tri-Charge Sharing Clock Scheme.

Authors: Jonalyn N. Gabutan

• 10-Bit Low Power Successive Approximation Register ADC for Wireless Sensor Networks

Authors: Sushima May M. Imperial and Jordan M. Juanday

• A High PSRR LDO Based on Feed Forward Ripple Cancellation Technique Implemented in 65nm Technology.

Authors: Marc Stephen Abellana and Ezra Christine Ypil

AY 2015-2016

• Delay-Locked Loop with Start-Controlled Phase-Frequency Detector

Authors: Renee Anne Albarracin, and Rafael Gamo

• Wifi Energy Harvester with Charge Control Mechanism

Authors: Kriz Kevin C. Adrivan, and Harris W. Guinomla

• FPGA Based Wireless Heart Rate and Body Temperature Measuring System

Authors: Kenneth Bryan Dagasdas, and Dean Jeremy Dagting

• A Design of Self-Biased Cross Cuopled Rectifier with Integrated Dual Threshold Voltage for RF Energy Harvesting Application

Authors: Mark Eric C. Andam, and Charlene Mae P. Canja

• CMOS RC Oscillator for Microcontroller Applications with Current Trimming Approach

Author: Garyl Jay N. Pepito

• Low Power Design of 4-KB SRAM Implemented in 65nm Technology

Authors: Mohamad Fahad Cader, and Kenneth Kyle Diez

• A gm/Id-based Subthreshold Operation Amplifier with Current Subtractor Adaptive Biasing Circuit

Author: Dave Darryl Ditucalan

• Design of Pulse Width Modulation/Pulse Frequency Modulation Mode for a Buck Converter in 65nm CMOS Process

Authors: Niña Kirstin L. Pacamalan, and Kenneth John P. Ibarra

• Design of Delay Line Time to Digital Converter Based Temperature Sensor.

Authors: Kathleen Kaye Alcuizar, and Robert Leemar M. Bagundol

AY 2014-2015

• Design of High Throughput and Low Power Cryptographic Core using Blowfish Algorithm

Author: Blesshe Mae Beron and Varrie Duhaylungsod

Remark: BEST PAPER in IEEE HNICEM 2019

• CMOS Implemented Trans Impedance Amplifier for Optical Communications

Author: Dessa Piandong

• Monolithic Microwave Integrated Circuit (MMIC) Design of Inverse Class-J Power Amplifier with Varactor Diode for High Efficiency in 4G Communications System

Authors: Krisha Dawn Dura and Chrizia Mae Nabua

• Gs/s Track-and Hold- Circuit in 90nm CMOS Process Technology

Author: Daryl S. Auguis

• Design of a Low-Power Internal Receiver Front-End Circuit for Wireless Downlink in Neural Prosthesis Implantable Medical Device

Author: Lovely Jane V. Vallinas

• Low Power Boost Converter for Pacemaker Energy Harvesting Application

Author: John Ray Chan

• Low Dropout Voltage Regulator for Vivo Biomedical Implantable Devices Implemented in 90nm CMOS Process Technology

Author: Camsia Minaga

• Comparison Between 90nm and 32nm CMOS Technology Implementation of Low Voltage Bandgap Reference with PSR Enhancement Stage.

Authors: Rhea Vanessa Acut and Sushimae Nabangue

• Filterless Class-D Amplifier

Author: Darwen Corgue and Kevin Maglinte

AY 2013-2014

• On-Chip Indoor Light Energy Harvester for Ultra-Low-Power Applications Implemented in 90nm CMOS Process Technology

Authors: Meilyssa A. Mayormita and John Raul C. Rebollos

• RF-to-DC Converter for Ultra-low Power Application

Authors: Marnier B. Bate and Emmanuel D. Talagon

• Integration Of OpenCV And Cyclone V Hybrid ARM and FPGA SoC for Face Detection Application

Author: Gil Michael E. Regalado

• A 500 MHz Fast-Locking Delay-Locked Loop with Linear Delay Element

Author: Larry Gerard G. Aquino and Leocarl M. Viñalon

• On-Chip CMOS Multi-Band Matching Circuit for RF Energy Harvesting

Author: Kento A. Fujimori and Keno Arnieldo T. Hibaya

• AM Transmitter Implemented in 0.18µm CMOS Process Technology

Author: Muhammad Shaheed D. Ibrahim and Mohammad Ali M. Muti

AY 2012-2013

• 18-bit Decimator Design for Sigma-Delta ADC with Variable Oversampling Rate for Audio Application

Author: Dominic O. Cagadas

• 3^rd, 4^th & 5^th Order Single-Stage Delta-Sigma Modulator for an 18-Bit Audio DAC.

Author: Jebien May Calapiz

• A 1.8V 640-MHz Phase Locked Loop as a Frequency Multiplier for Continuous-time Sigma-Delta ADC

Authors: Christina A. Garcia, and Stella Sofia I. Sabate

• A 1 GHz Delay-Locked Loop Using a 4-Cell Delay-Time with Extended Inverters

Authors: Vincent Heramiz, and Pleiades Longkit

• A Design for High Speed CMOS Fully Parallel Content-Addressable Memory

Authors: Kresil Joy Jimenez and Cris Tero

• Closed Loop Fractional Step-Down Charge Pump DC-DC Converter with Digital Control Design

Authors: Meliza C. Capino, and Lyneth N. Rivera

• High Efficiency Power Converter for RFID Application

Authors: Ultraviolet R. Morandante and Jourdan A. Mabayo

• Implementation of the Hard-Decision Algorithm Low-Density Parity Check Codes in a 0.13µm CMOS Process

Authors: Roberto Madronial, Jr. and Daryl Pongcol

• Design and Implementation of Universal Synchronous Asynchronous receiver Transmitter on Verilog HDL

Authors: Kramer C. Chua and Demie mae V. Dajao

AY 2011-2012

• PWM Boost Converter for Multi-Channel Constant-Current LED Driver

Authors: Meynard Hamak, and Aaron Kris Suizo

• 12-Bit Cascaded-Folding and Cascaded-Interpolating in 90nm CMOS Technology

Authors: Marjulyn Doce, Isovelle Lanz Embalsado, Loie Adrian Fernandez, and Alpe John Santos

• 2-1, 2-2 And 2-1-1 Mash Modulators for 18bit Audio DAC

Authors: John David Mangali, and Kenneth Harvey Duque

• Step-Down DC-DC Converter Charge Pump with Digital Control in 90nm CMOS Process Technology

Authors: John Ray Esic, and Van Louven Buot

• Protection Circuits (OTP,OCP & OVP) Design in 90nm CMOS Process Technology for DC-DC Converter

Authors: Jimmy Colaste, and Jennifer Ian Ligtao

• 125 MHz 16 X 16 SROM via Cell-Based

Authors: Saidaliah Sarip, and Quenie Alico

• 12-Bit Pipeline ADC-Implemented in 0.09-um Digital CMOS Technology for Powerline Alliance

Authors: Jayson Loreto, Sheerah Dale Orlasan, Lavern Bete, and Honey Mae Tagalogon

• Step-Down Charge Pump Design in 90nm CMOS Process with Enhance Voltage Regulation

Authors: Jenelyn Tiwanac, and Rochelle Sabarillo

• 10-bit High Resolution DAC with Fully Segmented Dynamic Element Matching

Authors: Michelle Batu, and Danielene Caberte

• 10-Bit Segmented Current-Steering DAC in CMOS 90nm Process

Authors: Franzymell Dy And Renato Bringas, Jr.

• 6-bit Flash ADC Using Interpolating Technique Implemented in 90nm CMOS Process

Authors: Leo Geralla, and Kimberly Mae Bayang

• Enhanced RF to DC Converter with LC Resonant Circuit

Authors: Lester Jandraux Gabrillo, and Mark Geoffray Gales

• High Speed Optical Receiver Front-End Implemented in 90nm CMOS Technology

Authors: Aprilyne Tiongson, and Gino O2 Gupana

• 1.2v, 3.3v 8-bit Sub-Ranging Flash ADC Using Pseudo-Dynamic with 1-GHz Clock Frequency

Authors: Arthur Garao, and Ronnie Asino

• 10-bit 90nm CMOS SAR ADC

Authors: Ace John Tiongco, and Jeffrey Armingol

• Full Custom Design of Split-Set Data Weighted Averaging for 3 bit Unit Elements Digital-Analog Converter

Author: Mark Cyril Jubay

AY 2010-2011

• Low Voltage Bandgap Reference With PSR Enhancement Stage Implemented in 90nm CMOS Technology

Author: Keith Francisco (BEST COLLEGE THESIS)

• Digital Implementation Of A 3-bit Digital-To-Analog Converter With Dynamic Element Matching Using Data Weighted Averaging For Linearity Enhancement

Authors: Christine Mendoza, and Oscar Balatero

• PWM Controlled Buck Converter For Multi-Channel Constant-Current LED Driver

Authors: Richmod Magallon, and Chenny Caberteja

• Different Digital Cancellation Logic (DCL) Design For Multistage Noise Shaping (MASH) 2.2/2.1/1.1 Analog-To-Digital (A/D) Converter

Author: Kent Dun Lagaras

• Comparison Between The Stability And Over-all Performance Of A Type II And Type III Compensation Network In A PWM Boost Converter

Author: Jameen Macabanding

• Two-Level Flash Time-To-Digital Converter For Period Measurement

Author: Mohammad Hudhaif Bin Shedique Alug

• Voltage-Mode Synchronous PWM/PFM Buck Converter

Authors: Geo Macana, and Jexter Babatugon

• Multi-Channel Constant-Current Led Driver With Boost Converter

Author: Meynard Hamak and Kris Suizo Aaron

• 18-Bit Audio Mash 2-2 Sigma Delta ADC

Authors: Tarhata Sandra Badelles, Gideon John Paza, and Kathy Venzon

• 18-Bit Delta-Sigma D/A Converter –5th Order Cascoded Modulator Architecture

Authors: Jessica Aileen Aldueso, Darwin Mangca, Cris Nickson Aleman, and Michael

Vincent Mosquera

• 3rd – Order Dual Truncation 18-Bit Audio Mash 2-1 Delta-Sigma DAC in 90nm CMOS Technology Implementation

Authors: Mycel Capilayan, Mark Laurence Dandan, and Sittie Aleyah Magayo-Ong

• 8-Bit DAC for Zilog Z8 Encore ADC

Authors: Daisy Caas, and Yitzhak Huevos

• 8-Bit DAC With Partial Randomization Dynamic Element Matching for Nonlinear Distortion Correction

Authors: Jose Ricardo Catane and Mark Jayson Mortel

• Power Efficiency Class D Amplifier

Author: Frandee Von Del Socorro

• Low Dropout Voltage Regulator Design In 90nm CMOS Technology Process

Author: Isaac Sammuel Arancon

• Low Power, Low Voltage Bandgap Reference Circuit in 90nm CMOS Technology Process

Author: Jefferson Piscos

• Modulator Design of an 18-Bit 3rd Order (2-1 MASH) Sigma-Delta ADC In 90nm CMOS Process

Authors: Kyle Kester Bahian, Lucernas, And Ruby Ann Sabugal

• Over-Current Protection Circuit for Buck DC-DC Converter Design in 90nm CMOS Technology Process

Author: Natasha Mae Jao

• PFM Controller Design in 90nm CMOS Process

Author: Emerson Santiago

• Pulse Width Modulation Controller For DC-DC Converter Implemented in 90nm CMOS Technology Process

Author: Adren Cartajenas

• Type III Compensator for Synchronous DC-DC Buck Converter using 90nm Process

Author: Marl Hussein Niñal

• Ultra-Low-Power Digitally-Controlled Oscillator For ADPLL For SOC Applications Described In Verilog HDL

Author: Aebeedec Jan Luciano